With the increasing frequency of signals used in modern communication links, unwanted effects such as cross talk, ringing, reflection, ISI, offset, clock jitter and the like, occur due to the distributed nature of the media which transports these signals. A major contributor in DC coupled lines is the differential input signal DC offset (differential offset in short) which is the combination result of different amplitudes and common modes on each line of the differential pair. The circuits that are used in the signal path, such as the drivers and receivers, the transporting media (e.g. transmission lines, . . . ) and the adaptation circuits therebetween, are the main causes to said differential offset.
A definition of the differential offset will be now given in conjunction with FIGS. 1A and 1B. FIG. 1A shows a differential signal VP and VM, respectively the potential applied on the positive and the negative legs or input terminals of a receiver, their difference (VP−VM) representing the data. As apparent in FIG. 1A, amplitudes and common modes are different into the assert phase (A) and negate or de-assert phase (N). These amplitudes are respectively labeled VPA/VMA and VMN/VPN, and will be referred to hereafter as the asserted data (state=1) and de-asserted data (state=0). The two common modes are shown in dotted lines. The differential offset Voff is equal to the half sum of the differential amplitude (VPA−VMA) in the assert phase and of the differential amplitude (VPN−VMN) in the negate phase and thus can be written in either one of the two relations Voff=((VPA+VPN)−(VMA+VMN))/2 or Voff=((VPA−VMA)+(VPn−VMN))2. The differential offset is represented in FIG. 1B.
As the signal frequency increases and/or the distance to communicate, and due to the limited bandwidth of the transporting media (or cost limitation), the signal amplitude and slew rate is much reduced so that the signal degradation, due to the differential offset, becomes prohibitive. The differential offset impact on the signal distortion is usually referred to as the timing asymmetry (abbreviated in Tasym). FIGS. 2A and 2B show a differential signal carrying a significant offset and its impact on the receiver logic output signal for a fast and slow transporting media respectively. A fast media (FIG. 2A) causes a high slew rate (Tasym=Voff/slew rate) while a slow media (FIG. 2B) causes a high attenuation (Tasym=(T/2)×Sin−1(Voff/Vamp), wherein Vamp is the amplitude of the signal, assuming it is perfectly sine-shaped. The timing asymmetry is responsible for closing the signal eye at the receiver output. The eye diagram is an important characteristic of high speed serial data links. Data jitter and/or phase error (skew) can significantly reduce the useful sampling window. This basically reduces the following sampling circuit tolerance to the jitter and could increase the bit error rate (BER). The generated timing asymmetry is proportional to the ratio of offset versus the input slew rate. For instance, pursuant to the SCSI standard for hard-disk applications, referred to as SCSI-pi5, the timing asymmetry is up to 900 ps (on both sides of the signal eye) to be compared to the 3.125 ns bit cell, this is closing the signal eye by about 57%. According to this standard, data are transported at 320 MHz, a 12 meter transporting media is used and a 16 device connection is supported. In such application, the differential offset on its own could close up to 50% of the signal eye, so that a compensation of the differential offset becomes mandatory. Other applications such as high speed point to point back plane communications will suffer from the same problem, the differential offset becomes prohibitive due to the media attenuation at speed above the GHz.
On the other hand, the jitter and ISI have also a detrimental effect on the closure of the signal eye. The effect of the jitter is to decrease the width of the time interval in which the data signal can be reliably sampled. The effect of the ISI is to add a delay on the data stream depending on the past values of the data. For high speed data transfers, this ISI can substantially decrease the capacity of the receivers to tolerate the random data jitter.
FIG. 3 shows a conventional receiver of the prior art referenced 10 connected as an interface between a bus 11 and a logic deskewer block 12. The deskewer block 12 is in charge of capturing the data at the best sampling point, then resynchronizing all bits together to rebuilt the original word. Now turning to FIG. 3, the conventional receiver 10 consists of an adaptator 13, an equalizer 14 and a comparator 15 that are connected in series. The comparator 15 is controlled by a digital to analog converter (DAC) 16. Adaptator 13 and equalizer 14 which form analog input amplifier 17 respectively perform level shifting attenuation and high frequency boosting. Such a receiver 10 is usually associated with a successive approximation register (SAR) 18 which is connected at the comparator 15 output. The role of the SAR 18 is to determine the offset compensation value and to hold it in dedicated registers. The combination of a DAC, a SAR and a comparator shown in FIG. 3 is known but only for the purpose of compensating the receiver offset by short circuiting its inputs. This compensation value labeled OS, which is determined and stored in the SAR 18, is applied to the DAC 16. In turn, DAC 16 generates a control signal named Cor_ofs which is applied to the comparator 15. In receiver 10, comparator 15 is a simple differential amplifier able to make the difference between the two components of the differential signal. For standard applications, i.e. other than SCSI-pi5, adaptor 13 and equalizer 14 are optional circuit blocks. The front end adaptor 13 can be very simple and the equalizer 14 may even be not used. There are known techniques to eliminate the differential offset in encoded data transmission techniques such as SONET or 8-to-10 encoding data, but not for non-encoded data like SCSI, that do not settle maximum run length (the signal bandwidth has no frequency limitations). Canceling only the receiver differential offset is easy to implement but it solves only 30% of its magnitude.
The conventional receiver 10 depicted in FIG. 3 will not be compliant with the SCSI-pi5 (T10) standard because it requests a very significant offset compensation capability (20 mV residual differential offset and Tasym lower than 200 ps). For instance, to date, conventional receivers exhibit Tasym values up to 900 ps that are to be compared to the 3.125 ns bit cell, so that the signal eye is closed by about 57%. Keeping in mind that the specification related to ISI (intersymbol interference) is very aggressive, such receivers could not be operative with this standard.